1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device which includes two interconnect layers (word line and bit line) formed over a semiconductor substrate, a capacitor formed over the interconnect layers, connection electrodes for connecting the bit line and the capacitor to the semiconductor substrate, and a transistor having a gate electrode serving as the word line.
2. Description of the Background Art
FIGS. 111 through 122 are cross-sectional views showing conventional steps of the fabrication of a semiconductor device (DRAM) in sequential order. First, an isolation insulative film 2 is formed on a semiconductor (e.g., Si) substrate 1 by the LOCOS technique, and laminated structures each comprised of a gate oxide film 3, a gate electrode 4, and an insulative film 5 are selectively formed on the semiconductor substrate 1 except where the isolation insulative film 2 is formed (FIG. 111). The gate electrodes 4 are to function as word lines of the DRAM. Then, a silicon oxide film 6 having a thickness of, for example, some hundreds of nanometers is formed over the top surface by the CVD process (FIG. 112).
Anisotropic oxide etching which provides a high etching rate in a direction perpendicular to the semiconductor substrate 1 is performed to leave parts of the silicon oxide film 6 on side walls of the gate oxide films 3, gate electrodes 4, and insulative films 5 to form sidewalls 6a to 6f. Ion implantation is performed using the insulative films 5 and the sidewalls 6a to 6f as a mask to form source/drain regions 261 to 263 in the semiconductor substrate 1 (FIG. 113).
A silicon oxide film is deposited over the top surface by the CVD process to form an interlayer insulative film 8 having a thickness of, for example, some hundreds of nanometers (FIG. 114). A photoresist 10 having a predetermined pattern is formed on the interlayer insulative film 8 by the conventional transfer process. Using the photoresist 10 as a mask, the interlayer insulative film 8 is subjected to an etching process which forms a contact hole 50 to expose the source/drain region 262. Then, the photoresist 10 is removed (FIG. 115).
A conductive film 9 of WSi/poly Si, TiSi/poly Si and the like is formed for connection to the source/drain region 262 through the contact hole 50 (FIG. 116). The conductive film 9 is to function as a bit line of the DRAM.
A silicon oxide film, for example, is deposited over the top surface by the CVD process to form an interlayer insulative film 11 (FIG. 117). A photoresist 12 having a predetermined pattern is formed on the interlayer insulative film 11 by the conventional transfer process (FIG. 118).
Etching the interlayer insulative films 11 and 8 by the same etchant using the photoresist 12 as a mask forms a contact hole 51 to expose the source/drain region 261. Then, the photoresist 12 is removed (FIG. 119).
Poly Si is deposited by the CVD process so as to fill the contact hole 51 to form a capacitor lower electrode 13. The capacitor lower electrode 13 is connected to the source/drain region 261 through the contact hole 51. A Si.sub.3 N.sub.4 film is deposited over the top surface to form a capacitor dielectric film 14. Poly Si is deposited on the capacitor dielectric film 14 by the CVD process to form a capacitor upper electrode 15 (FIG. 120).
An interlayer insulative film 16 made of, for example, silicon oxide is formed on the capacitor upper electrode 15 by the CVD process (FIG. 121). Interconnect layers 17 made of, for example, AlCu and AlSiCu are selectively formed on the interlayer insulative film 16 (FIG. 122).
The background art method of fabricating the semiconductor device, however, involves the need to etch the silicon oxide film which is as thick as some hundreds of nanometers when the sidewalls 6a to 6f are formed to cause difficulties in etching control, resulting in damages to the surface of the semiconductor substrate 1 due to overetching. Additionally, the surface of the semiconductor substrate 1 is also damaged by overetching when the contact holes 50 and 51 are formed. In this fashion, crystal defects 25 have been created adjacent the source/drain regions 261 and 262 (FIGS. 113 through 122). The crystal defects 25 induce leakage currents to cause the device to malfunction.
For instance, the DRAM is required to re-write (refresh) data stored in memory cells thereof at regular time intervals. The presence of the crystal defect 25 adjacent the source/drain region 261 connected to the capacitor lower electrode 13 causes the electric charges accumulated in the capacitor lower electrode 13 to flow away as a leakage current toward the semiconductor substrate 1, making it impossible to re-write proper data.
Furthermore, misalignment of the pattern of the gate electrodes 4 and the photoresist 10 due to process variations in the step of forming the photoresist 10 results in contact between the conductive film 9 serving as the bit line and the gate electrodes 4 serving as the word lines as shown in FIG. 116, leading to device malfunctions.